This invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to an isolation technology in semiconductor devices such as a DRAM, an EEPROM, etc.
With further miniaturization of elements in semiconductor devices, an isolation method has become one of the critical problems to be overcome. A method known as local oxidation of silicon (LOCOS) has been widely used as the isolation method. When isolation is carried out by this LOCOS method, however, bird's beaks develop and limit the area of forming elements such as transistors. Therefore, this method cannot easily satisfy a higher integration density of semiconductor devices required recently. A so-called "field-shield isolation" method, which isolates elements by a MOS structure formed on a semiconductor substrate, has been proposed as an isolation method which does not generate the bird's beaks.
Generally, the field-shield isolation structure has a MOS structure in which shield gate electrodes made of a polycrystalline silicon (poly-silicon) film are formed over a silicon substrate through a shield gate oxide film. This shield gate electrode is always kept at a constant potential of 0 V, for example, as it is grounded (GND) through a connection conductor when the silicon substrate (or a well region) has a P type conductivity. When the silicon substrate (or the well region) has an N type conductivity, the shield gate electrode is always kept at a predetermined potential (a power source potential Vcc [V], for example).
As a result, because the formation of a channel of a parasitic MOS transistor on the surface of the silicon substrate immediately below the shield gate electrode can be prevented, adjacent elements such as transistors can be electrically isolated from one another. According to this field-shield isolation, ion implantation for forming the channel stopper which has been necessary for the LOCOS is not necessary. In consequence, a narrow channel effect of the transistor can be reduced and the substrate concentration can be lowered, so that the junction capacitance formed inside the substrate becomes small, and the operation speed of the transistor can be improved.
JP-A-61-75555 (laid-open on Apr. 17, 1986 and corresponding to U.S. Ser. No. 626,572 filed Jul. 2, 1984 with U.S. PTO) discloses a semiconductor device employing a field-shield structure or field oxide film for isolation between elements.
JP-A-63-305548 (laid-open on Dec. 13, 1988) discloses a semiconductor device in which a field oxide film is formed on an n-type semiconductor region and a field-shield structure is formed on a p-type semiconductor region.